Researchers have developed a technique to create a 3D chip with layers of semiconducting materials stacked directly atop one another. This new approach removes the need for thick silicon substrates in between layers, resulting in enhanced computation speed and efficiency, crucial for applications such as advanced AI hardware.
The electronics sector is nearing the maximum limit for the number of transistors that can fit on a computer chip’s surface. As a result, chip manufacturers are shifting their focus from making chips wider to making them taller.
Instead of continually reducing the size of transistors on a single layer, the industry now aims to stack multiple layers of transistors and semiconductors—similar to transforming a single-storey home into a skyscraper. These multilayer chips could process significantly more data and perform more complicated functions than conventional electronics can handle.
One of the main challenges in this progression is the foundational platform for these chips. Currently, large silicon wafers are the standard base for growing high-quality, single-crystalline semiconductor layers. Each layered chip would require substantial silicon “flooring” within each layer, which would hinder rapid communication between the semiconductor layers.
MIT engineers have now discovered a method to overcome this obstacle, creating a multilayer chip design that operates without any silicon wafer substrates and functions at low temperatures, thus protecting the circuits beneath.
The findings, published in the journal Nature, describe how the team successfully fabricated a multilayered chip featuring high-quality semiconductor materials stacked directly on each other.
This innovative method allows engineers to create high-performance transistors and memory elements on any crystalline surface, eliminating the dependence on large silicon wafers as a scaffold. By removing these bulky substrates, communication between the stacked semiconductor layers is significantly improved, leading to faster computation, according to the researchers.
The researchers anticipate that this technique could pave the way for AI hardware, enabling stacked chips suitable for laptops or wearable technology that could match the speed and power of current supercomputers while possessing data storage capacities comparable to that of physical data centers.
“This advancement presents vast opportunities for the semiconductor industry, allowing chips to be layered without the traditional constraints,” states Jeehwan Kim, the study’s author and a mechanical engineering associate professor at MIT. “This could result in meticulous improvements in computing power, particularly for AI applications, logic functions, and memory storage.”
The co-authors from MIT include Ki Seok Kim (first author), Seunghwan Seo, Doyoon Lee, Jung-El Ryu, Jekyung Kim, Jun Min Suh, June-chul Shin, Min-Kyu Song, Jin Feng, and Sangho Lee, along with partners from Samsung Advanced Institute of Technology, Sungkyunkwan University in South Korea, and the University of Texas at Dallas.
Seed pockets
Earlier in 2023, Kim’s team established a technique to grow high-quality semiconductor materials on non-uniform surfaces, mimicking the varied surfaces of semiconductor circuitry on completed chips. They utilized transition-metal dichalcogenides, or TMDs—2D materials regarded as potential alternatives to silicon for constructing smaller, high-efficiency transistors. These 2D materials can retain their semiconductor properties even at the atomic scale, where silicon’s effectiveness drops noticeably.
Previously, their group had grown TMDs on silicon wafers with artificial coatings and over existing TMDs. To achieve orderly, single-crystalline arrangements instead of random polycrystalline formations, Kim and colleagues first applied a thin film of silicon dioxide as a mask on the silicon wafer, with tiny openings, or “pockets.” By exposing this mask to a gas of atoms, they discovered atom “seeds” formed in the pockets, promoting orderly growth.
However, this technique only functioned at about 900 degrees Celsius at the time.
“If we grow this single-crystalline material above 400 Celsius, it damages the underlying circuitry,” Kim clarifies. “Our challenge was to adapt this technique to work below 400 Celsius for significant impact.”
Building up
In their most recent efforts, Kim and his team worked on fine-tuning their approach to grow single-crystalline 2D materials at sufficiently low temperatures to protect the circuitry underneath. They found that a straightforward answer lay within metallurgy—the art and science of metalwork. When molten metal is poured into a mold, it “nucleates,” or forms grains that merge to create a consistent crystal structure. Metallurgists have recognized that nucleation occurs more efficiently at the edges of the mold.
“It’s established that edge nucleation requires less energy—thus, less heat,” Kim comments. “We applied this concept from metallurgy to pave the way for future AI hardware.”
The team targeted growing single-crystalline TMD on a silicon wafer that already contained transistor circuits. They masked the circuitry similarly to their previous methods and then placed TMD “seeds” at the edges of each pocket. They found that these seeds grew into single-crystalline structures at temperatures as low as 380 degrees Celsius, while those located in the pocket centers required higher temperatures.
Going further, the researchers employed this new method to create a multilayer chip with alternating layers of two types of TMD—molybdenum disulfide, a candidate for n-type transistors, and tungsten diselenide, which holds potential for p-type transistors. Both types of transistors form the essential components for executing logical operations, and the team successfully produced these materials in single-crystalline form stacked on top of one another, negating the need for intervening silicon wafers. Kim asserts that this approach could effectively double the density of a chip’s semiconducting elements, particularly in metal-oxide semiconductors (CMOS), fundamental to modern logic circuits.
“What we’ve created is not just a 3D logic chip, but also a combination of 3D memory and logic layers,” Kim explains. “With our method, it’s possible to layer numerous logic and memory elements atop one another, facilitating exceptional communication.”
“Conventional 3D chips typically involve silicon wafers placed in between layers, requiring drilling holes that limit the number of stacked layers, alignment precision, and yields,” adds first author Kiseok Kim. “Our growth-based approach addresses all these challenges simultaneously.”
To advance the commercialization of their stackable chip design, Kim has founded a company named FS2 (Future Semiconductor 2D materials).
This study received partial support from Samsung Advanced Institute of Technology and the Air Force Office of Scientific Research.
